1. Field of the Invention
The present invention relates to a semiconductor device having a gate electrode and its manufacturing method, and particularly to a technique for thinning the gate electrode.
2. Description of the Background Art
The requirements of making finer circuit patterns for more highly integrated semiconductor devices are constantly bringing about finer gate electrode structures. Also, the technique for reducing the gate length (channel length) of transistors, i.e. for thinning the gate electrode structures, is important for the purpose of increasing the speed of devices. However, since the resolution in lithography is limited by the limited wavelength of the light source, it is difficult to form gate electrodes having widths of about 100 nm or less by using common gate electrode formation process; therefore the methods shown below are used to form such thin gate electrodes.
FIGS. 22A, 22B, 23A, 23B, 24A and 24B are process diagrams showing a conventional semiconductor device manufacturing method. In these drawings, FIG. 22B shows the cross section taken along the direction P1-Q1 in FIG. 22A, FIG. 23B shows the cross section taken along the direction P2-Q2 in FIG. 23A, and FIG. 24B shows the cross section taken along the direction P3-Q3 in FIG. 24A. First, as shown in FIGS. 22A and 22B, a gate oxide film 103 and a gate electrode material film 104 are formed on a silicon substrate having an active region 101 and isolation oxide films 102, and a resist mask 105, in the shape of a line crossing the active region 101, is formed thereon by lithography. Next, the resist mask 105 is lightly ashed and thus slimmed (thinned). This results in, as shown in FIGS. 23A and 23B, a resist mask 105a of a reduced width (hereinafter referred to as a thinned resist mask). Then the gate electrode material film 104 is anisotropically etched using the thinned resist mask 105a as a mask, so as to form a thinned gate electrode 104a as shown in FIGS. 24A and 24B.
Clearly, the gate electrode 104a thus obtained has a smaller width than the resist mask 105 shown in FIGS. 22A and 22B which was formed by lithography and which has not yet been thinned. This means that the width of the gate electrode 104a can be reduced beyond the limit of resolution in the lithography technique. As can be seen from FIGS. 24A and 24B, thinning the gate electrode and reducing its width shortens the gate length (channel length) of the transistor, which contributes to achievement of higher operation speed of the semiconductor device.
FIGS. 25A and 25B are diagrams used to describe a problem of this conventional semiconductor device. FIG. 25A is the top view of the semiconductor device having the thinned gate electrode 104a shown in FIG. 24A, and FIG. 25B is an enlarged view of the part Z in FIG. 25A, where the broken line 115 shows the shape of the resist mask 105 of FIG. 22A which are not yet thinned. The ashing process for thinning the resist mask 105 in this method reduces the entire dimensions of the resist mask 105. That is to say, the resist mask 105 is made smaller not only in the width direction but also in the length direction to form the thinned resist mask 105a. Accordingly, as shown in FIG. 25B, the length of the resultant gate electrode 104a is shorter by dS than the length of the resist mask 105 not thinned yet. As a countermeasure, it may be suggested that, prior to the process of thinning the gate electrode, a longer resist mask 105 be formed before it is thinned, considering the lengthwise size reduction. However, forming a longer resist mask 105 increases the chip size and therefore hinders achievement of higher integration of the semiconductor device.
FIGS. 26A, 26B, 27A, 27B, 28A, 28B, 29A and 29B are process diagrams showing another conventional semiconductor device manufacturing method. In these drawings, FIG. 26B shows the cross section taken along the direction P4-Q4 in FIG. 26A, FIG. 27B shows the cross section taken along the direction P5-Q5 in FIG. 27A, and FIG. 28B shows the cross section taken along the direction P6-Q6 in FIG. 28A. FIG. 29B shows the cross section taken along the direction P7-Q7 in FIG. 29A. First, as shown in FIGS. 26A and 26B, a gate oxide film 103, a gate electrode material film 104, and a hard mask material film 106 of, e.g. SiO2, are formed on a silicon substrate having an active region 101 and isolation oxide films 102, and a resist mask 107 in the shape of a line crossing the active region 101 is formed thereon by lithography. Then the hard mask material film 106 is etched by using the resist mask 107 as a mask to form a hard mask 106a as shown in FIGS. 27A and 27B. Next, the hard mask 106a is thinned by isotropic etching, e.g. wet etching. This results in a hard mask 106b of a reduced width (hereinafter referred to as a thinned hard mask) as shown in FIGS. 28A and 28B. Then the gate electrode material film 104 is anisotropically etched using the thinned hard mask 106b as a mask, so as to form a thinned gate electrode 104b as shown in FIGS. 29A and 29B.
The process of thinning the hard mask 106a in this method provides the thinned hard mask 106b which has been made smaller not only in the width direction but also in the length direction than the hard mask 106a not thinned yet. That is to say, the resultant gate electrode 104b, too, is shorter in length than the hard mask 106a not thinned yet. That is, this manufacturing method, too, raises the problem described referring to FIGS. 25A and 25B.
As described above, the gate electrode thinning techniques in the conventional semiconductor device manufacturing methods involve a reduction of the length of the gate electrode. This requires that the gate electrode be designed longer in advance, considering the reduction of length (i.e. in the processes shown above, forming a longer resist mask 105 (or 107) before it is thinned), or that larger pads be designed at both ends of the gate electrode to which interconnections are connected, but such approaches result in an increase in chip size.